Daisaburo Takashima

According to our database, Daisaburo Takashima authored at least 27 papers between 1990 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs.

Ryu Ogiwara, Daisaburo Takashima, Sumiko M. Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga

IEEE J. Solid State Circuits, 2015

A 7T-SRAM with data-write technique by capacitive coupling.

Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2012

Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee.

Joo-Sun Choi, Daisaburo Takashima

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.

Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

IEEE J. Solid State Circuits, 2011

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell.

Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki

IEEE J. Solid State Circuits, 2011

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance.

Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii

IEEE J. Solid State Circuits, 2011

An embedded DRAM technology for high-performance NAND flash memories.

Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Future system and memory architectures: Transformations by technology and applications.

Nicky Lu, Leland Chang, Daisaburo Takashima

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.

Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii

IEEE Trans. Very Large Scale Integr. Syst., 2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

IEEE J. Solid State Circuits, 2010

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM.

Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2006

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.

Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

A 32-Mb chain FeRAM with segment/stitch array architecture.

Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr

IEEE J. Solid State Circuits, 2003

2002

A cell transistor scalable DRAM array architecture.

Daisaburo Takashima, Hiroaki Nakano

IEEE J. Solid State Circuits, 2002

2001

A 76-mm² 8-Mb chain ferroelectric memory.

Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki

IEEE J. Solid State Circuits, 2001

1999

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive.

Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka

IEEE J. Solid State Circuits, 1999

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.

Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1998

High-density chain ferroelectric random access memory (chain FRAM).

Daisaburo Takashima, Iwao Kunishima

IEEE J. Solid State Circuits, 1998

1997

A novel power-off mode for a battery-backup DRAM.

Daisaburo Takashima, Yukihito Oowaki

IEEE J. Solid State Circuits, 1997

1994

Standby/active mode logic for sub-1-V operating ULSI memory.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango

IEEE J. Solid State Circuits, April, 1994

Open/folded bit-line arrangement for ultra-high-density DRAM's.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi

IEEE J. Solid State Circuits, April, 1994

1993

An experimental DRAM with a NAND-structured cell.

Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka

IEEE J. Solid State Circuits, November, 1993

Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs.

Daisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara

IEEE J. Solid State Circuits, April, 1993

1992

Word-line architecture for highly reliable 64-Mb DRAM.

Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, April, 1992

1991

A 33-ns 64-Mb DRAM.

Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, November, 1991

1990

The stabilized reference-line (SRL) technique for scaled DRAMs.

Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, February, 1990