Damien Hardy

According to our database1, Damien Hardy authored at least 26 papers between 2007 and 2023.

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Bibliography

2023
SAMVA: Static Analysis for Multi-fault Attack Paths Determination.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2023

2021
TRAITOR: A Low-Cost Evaluation Platform for Multifault Injection.
Proceedings of the ASSS '21: Proceedings of the 2021 International Symposium on Advanced Security on Software and Systems, 2021

2020
NOP-Oriented Programming: Should we Care?
Proceedings of the IEEE European Symposium on Security and Privacy Workshops, 2020

2019
Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation.
Real Time Syst., 2019

2017
The Heptane Static Worst-Case Execution Time Estimation Tool.
Proceedings of the 17th International Workshop on Worst-Case Execution Time Analysis, 2017

Quantifying WCET reduction of parallel applications by introducing slack time to limit resource contention.
Proceedings of the 25th International Conference on Real-Time Networks and Systems, 2017

Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Speeding up Static Probabilistic Timing Analysis.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2014
On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

2013
Static probabilistic worst case execution time estimation for architectures with faulty instruction caches.
Proceedings of the 21st International Conference on Real-Time Networks and Systems, 2013

An analytical framework for estimating TCO and exploring data center design space.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

2012
Optimizing Data-Center TCO with Scale-Out Processors.
IEEE Micro, 2012

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Thermal characterization of cloud workloads on a power-efficient server-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
WCET analysis of instruction cache hierarchies.
J. Syst. Archit., 2011

Scalable Fixed-Point Free Instruction Cache Analysis.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

2010
Analyse pire cas pour processeur multi-cœurs disposant de caches partagés.
PhD thesis, 2010

2009
WCET Analysis of Multi-Level Set-Associative Data Caches.
Proceedings of the 9th Intl. Workshop on Worst-Case Execution Time Analysis, 2009

Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches.
Proceedings of the 30th IEEE Real-Time Systems Symposium, 2009

2008
WCET analysis of multi-level set-associative instruction caches
CoRR, 2008

WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches.
Proceedings of the 29th IEEE Real-Time Systems Symposium, 2008

Predictable Code and Data Paging for Real Time Systems.
Proceedings of the 20th Euromicro Conference on Real-Time Systems, 2008

2007
Predictable Paging in Real-Time Systems: A Compiler Approach.
Proceedings of the 19th Euromicro Conference on Real-Time Systems, 2007


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