Daniel Etiemble

CoRR, 2022

Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders.

[BibT_eX]

[DOI]

CoRR, 2022

CNTFET quaternary multipliers are less efficient than the corresponding binary ones.

[BibT_eX]

[DOI]

CoRR, 2022

Technologies and Computing Paradigms: Beyond Moore's law?

[BibT_eX]

[DOI]

CoRR, 2022

2021

Best CNTFET Ternary Adders?

[BibT_eX]

[DOI]

CoRR, 2021

2020

Multivalued circuits and Interconnect issues.

[BibT_eX]

[DOI]

CoRR, 2020

Comparing quaternary and binary multipliers.

[BibT_eX]

[DOI]

CoRR, 2020

Best implementations of quaternary adders.

[BibT_eX]

[DOI]

CoRR, 2020

Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits".

[BibT_eX]

[DOI]

IEEE Access, 2020

2019

Comparing ternary and binary adders and multipliers.

[BibT_eX]

[DOI]

CoRR, 2019

Ternary circuits: why R=3 is not the Optimal Radix for Computation.

[BibT_eX]

[DOI]

CoRR, 2019

Coprocessors: failures and successes.

[BibT_eX]

[DOI]

CoRR, 2019

Evolution of Technologies and Multivalued Circuits.

[BibT_eX]

[DOI]

CoRR, 2019

2018

Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors.

[BibT_eX]

[DOI]

Laurent Cabaret

J. Real Time Image Process., 2018

45-year CPU evolution: one law and two equations.

[BibT_eX]

[DOI]

CoRR, 2018

2017

Distanceless label propagation: An efficient direct connected component labeling algorithm for GPUs.

[BibT_eX]

[DOI]

Laurent Cabaret

Andrés Romero Mier y Terán

Proceedings of the Seventh International Conference on Image Processing Theory, 2017

2016

Automatic Task-Based Code Generation for High Performance Domain Specific Embedded Language.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2016

A new SIMD iterative connected component labeling algorithm.

[BibT_eX]

[DOI]

Proceedings of the 3rd Workshop on Programming Models for SIMD/Vector Processing, 2016

2015

Color tracking with contextual switching: real-time implementation on CPU.

[BibT_eX]

[DOI]

Florence Laguzet

Michèle Gouiffès

J. Real Time Image Process., 2015

Parallel light speed labeling: An efficient connected component labeling algorithm for multi-core processors.

[BibT_eX]

[DOI]

Laurent Cabaret

Fernando Machado Mendonca

Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014

High level transforms for SIMD and low-level computer vision algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2014 Workshop on Programming models for SIMD/Vector processing, 2014

2013

Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++.

[BibT_eX]

[DOI]

Khaled Hamidouche

Joel Falcou

Alba Cristina Magalhaes Alves de Melo

Andrés Romero Mier y Terán

Int. J. Parallel Program., 2013

High level tranforms toreduce energy consumption of signal and image processing operators.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

2012

Impact of high level transforms on high level synthesis for motion detection algorithm.

[BibT_eX]

[DOI]

O. Florent

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011

Embedded MRAM for high-speed computing.

[BibT_eX]

[DOI]

Weisheng Zhao

Yue Zhang

Yahya Lakys

Jacques-Olivier Klein

Luis Vitório Cargnini

Raphael Martins Brum

Yoann Guillemenet

Gilles Sassatelli

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.

[BibT_eX]

[DOI]

Weisheng Zhao

Lionel Torres

Luis Vitório Cargnini

Jacques-Olivier Klein

Dafine Ravelosona

Claude Chappert

Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

A framework for an automatic hybrid MPI+OpenMP code generation.

[BibT_eX]

[DOI]

Khaled Hamidouche

Joel Falcou

Fernando Machado Mendonca

Proceedings of the 2011 Spring Simulation Multi-conference, 2011

Parallel Biological Sequence Comparison on Heterogeneous High Performance Computing Platforms with BSP++.

[BibT_eX]

[DOI]

Khaled Hamidouche

Joël Falcou

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

Automatic color space switching for robust tracking.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Signal and Image Processing Applications, 2011

A small footprint interleaved multithreaded processor for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

AHDAM: An Asymmetric Homogeneous with Dynamic Allocator Manycore Chip.

[BibT_eX]

[DOI]

Charly Bechara

Nicolas Ventroux

Proceedings of the Facing the Multicore - Challenge II, 2011

Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems.

[BibT_eX]

[DOI]

Charly Bechara

Nicolas Ventroux

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Towards a parameterizable cycle-accurate ISS in ArchC.

[BibT_eX]

[DOI]

Charly Bechara

Nicolas Ventroux

Proceedings of the 8th ACS/IEEE International Conference on Computer Systems and Applications, 2010

2009

Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor.

[BibT_eX]

[DOI]

Proceedings of the PACT 2009, 2009

2005

Des flottants 16 bits sur microprocesseurs d'usage général pour images et multimédia.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2005

Customizing 16-bit FP Instructions on a NIOS II Processor for FPGA Image and Media Processing.

[BibT_eX]

[DOI]

Samir Bouaziz

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

16-bit Floating Point Instructions for Embedded Multimedia Applications.

[BibT_eX]

[DOI]

S. A. Ould Kablia

Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004

16-Bit FP Sub-Word Parallelism to Facilitate Compiler Vectorization and Improve Performance of Image and Media Processing.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004

2003

Why M-Valued Circuits are Restricted to a Small Niche.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2003

2002

MPI ou MPI+OpenMP sur grappes de multiprocesseurs?

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2002

Computer arithmetic and hardware: "off the shelf" microprocessors versus "custom hardware".

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2002

Optimizing DSP and media benchmarks for Pentium 4: hardware and software issues.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Numerical Applications and Sub-Word Parallelism: The NAS Benchmarks on a Pentium 4.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

2001

Understanding performance of SMP clusters running MPI programs.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2001

2000

MPI versus MPI+OpenMP on IBM SP for the NAS Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing 2000, 2000

Investigating the Performance of Two Programming Models for Clusters of SMP PCs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

Performance Evaluation of Two Programming Models for a Cluster of PC Biprocessors.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Performance of the NAS Benchmarks on a Cluster of SMP PCs Using a Parallelization of the MPI Programs with OpenMP.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing Technologies, 1999

1997

An HPF Case Study of a Domain-Decomposition Based Irregular Application.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing Technologies, 1997

Communications in Parallel Architectures and Networks of Workstations: From Standardisation to New Standards.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing Technologies, 1997

Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces.

[BibT_eX]

[DOI]

A. Pavlov

Proceedings of the 23rd EUROMICRO Conference '97, 1997

Complete x86 instruction trace generation from hardware bus collect.

[BibT_eX]

[DOI]

P. Bosch

A. Carloganu

Proceedings of the 23rd EUROMICRO Conference '97, 1997

1995

Standard Microprocessors Versus Custom Processing Elements for Massively Parallel Architectures.

[BibT_eX]

[DOI]

Cécile Germain

Proceedings of the Parallel Computing Technologies, 1995

From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Parallel architecture and language in Europe.

[BibT_eX]

[DOI]

Jean-Claude Syre

Future Gener. Comput. Syst., 1994

Performance of CMOS Current Mode Full Adders.

[BibT_eX]

[DOI]

A. Kazeminejad

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

CML Current Mode Full Adders for 2.5-V Power Supply.

[BibT_eX]

[DOI]

A. Kazeminejad

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

Hardware features of the static communication network of a parallel architecture.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

A Communication Architecture for a Massively Parallel Message-Passing Multicomputer.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 1993

A Parralel Architecture Based on Compiled Communication Schemes.

[BibT_eX]

Franck Delaplace

Damien Gautier de Lahaut

Proceedings of the Parallel Computing: Trends and Applications, 1993

A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

Balanced Distributed Memory Parallel Computers.

[BibT_eX]

[DOI]

Proceedings of the 1993 International Conference on Parallel Processing, 1993

Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system.

[BibT_eX]

[DOI]

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992

On the Performance of Multivalued Integrated Circuits: Past, Present and Future.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

3D hardware packages for parallel architectures.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1991

1990

A risc central processing unit for a massivelly parallel architecture.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1990

4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture.

[BibT_eX]

[DOI]

Christophe Chanussot

Vincent Néri

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1988

Comparison of Binary and Multivalued ICs According to VLSI Criteria.

[BibT_eX]

[DOI]

Michel Israël

Computer, 1988

A highly parallel processor with an instruction set including relational algebra.

[BibT_eX]

[DOI]

Pascal Faudemay

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987

The Database Processor 'RAPID'.

[BibT_eX]

[DOI]

Proceedings of the Database Machines and Knowledge Base Machines, 1987

1984

Micro-computer oriented algorithms for delay evaluation of MOS gates.

[BibT_eX]

[DOI]

Proceedings of the 21st Design Automation Conference, 1984

1980

Multivalued I<sup>2</sup>L Circuits for TSC Checkers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1980

1978

TTL circuits for a 4-valued bus a way to reduce package and interconnections.

[BibT_eX]

[DOI]

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

1977

Implementation of Ternary Circuits with Binary Integrated Circuits.

[BibT_eX]

[DOI]