David Roberts

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.


Evaluation of Activated Carbon and Platinum Black as High-Capacitance Materials for Platinum Electrodes.
Sensors, 2022

Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Reliability-Aware Data Placement for Heterogeneous Memory Architecture.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Canine-Centered Computing.
Found. Trends Hum. Comput. Interact., 2017

A reconfigurable wideband streaming channeliser for RF sensing applications: A multiple GPU-based implementation.
Proceedings of the 11th International Conference on Signal Processing and Communication Systems, 2017

Reliability and Performance Trade-off Study of Heterogeneous Memories.
Proceedings of the Second International Symposium on Memory Systems, 2016

Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

HpMC: An Energy-aware Management System of Multi-level Memory Architectures.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

NMI: A new memory interface to enable innovation.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

Toward efficient programmer-managed two-level memory hierarchies in exascale computers.
Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014

Distribution network voltage control using energy storage and demand side response.
Proceedings of the 3rd IEEE PES Innovative Smart Grid Technologies Europe, 2012

A limits study of benefits from nanostore-based future data-centric system architectures.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

MobSens: Making Smart Phones Smarter.
IEEE Pervasive Comput., 2009

Integrating NAND flash devices onto servers.
Commun. ACM, 2009

Scratchpads: a data-publishing framework to build, share and manage information on the diversity of life.
BMC Bioinform., 2009

Using non-volatile memory to save energy in servers.
Proceedings of the Design, Automation and Test in Europe, 2009

On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology.
Microprocess. Microsystems, 2008

Improving NAND Flash Based Disk Caches.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

A Conceptual Framework for Modelling Crowd Behaviour.
Proceedings of the 11th IEEE International Symposium on Distributed Simulation and Real-Time Applications, 2007

A self-tuning DVS processor using delay-error detection and correction.
IEEE J. Solid State Circuits, 2006

Error Analysis for the Support of Robust Voltage Scaling.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling.
Proceedings of the 2004 Design, 2004

Distributed Process Networks in Java.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

System design for a low cost PA-RISC desktop workstation.
Proceedings of the Compcon Spring '91, San Francisco, 1991

An ECL RISC multiprocessor.
Proceedings of the Compcon Spring '91, San Francisco, 1991

Knowledge Creation by Information Retrieval.
J. Documentation, 1990

An ECL RISC microprocessor designed for two level cache.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990