Ender Yilmaz

According to our database1, Ender Yilmaz authored at least 30 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops.
ACM Trans. Design Autom. Electr. Syst., 2021

2019
Adaptive Test for RF/Analog Circuit Using Higher Order Correlations among Measurements.
ACM Trans. Design Autom. Electr. Syst., 2019

Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Online information utility assessment for per-device adaptive test flow.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Enabling fast process variation and fault simulation through macromodelling of analog components.
Proceedings of the 27th IEEE North Atlantic Test Workshop, 2018

Design of aging aware 5 Gbps LVDS transmitter for automotive applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Built-in self-test for stability measurement of low dropout regulator.
Proceedings of the IEEE International Test Conference, 2017

Evaluation of loop transfer function based dynamic testing of LDOs.
Proceedings of the International Test Conference in Asia, 2017

2015
Adaptive-Learning-Based Importance Sampling for Analog Circuit DPPM Estimation.
IEEE Des. Test, 2015

2014
Built-In EVM Measurement With Negligible Hardware Overhead.
IEEE Des. Test, 2014

2013
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Efficient Process Shift Detection and Test Realignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Adaptive quality binning for analog circuits.
Proceedings of the 18th IEEE European Test Symposium, 2013

Fault analysis and simulation of large scale industrial mixed-signal circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive reduction of the frequency search space for multi-vdd digital circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Electrical calibration of spring-mass MEMS capacitive accelerometers.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Test Application for Analog/RF Circuits With Low Computational Burden.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Adaptive testing: Conquering process variations.
Proceedings of the 17th IEEE European Test Symposium, 2012

Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
An industrial case study of analog fault modeling.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Adaptive multidimensional outlier analysis for analog and mixed signal circuits.
Proceedings of the 2011 IEEE International Test Conference, 2011

Fast and Accurate DPPM Computation Using Model Based Filtering.
Proceedings of the 16th European Test Symposium, 2011

2010
Adaptive test flow for mixed-signal/RF circuits using learned information from device under test.
Proceedings of the 2011 IEEE International Test Conference, 2010

Accurate multi-specification DPPM estimation using layered sampling based simulation.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Analog Layout Generator for CMOS Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Built-in EVM measurement for OFDM transceivers using all-digital DFT.
Proceedings of the 2009 IEEE International Test Conference, 2009

Defect-based test optimization for analog/RF circuits for near-zero DPPM applications.
Proceedings of the 27th International Conference on Computer Design, 2009

Adaptive test elimination for analog/RF circuits.
Proceedings of the 46th Design Automation Conference, 2009

2008
Dynamic test scheduling for analog circuits for improved test quality.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
New layout generator for analog CMOS circuits.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007


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