Eric Martin

Affiliations:
  • Université de Bretagne-Sud


According to our database1, Eric Martin authored at least 70 papers between 1993 and 2023.

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Bibliography

2023
How Humans Comply With a (Potentially) Faulty Robot: Effects of Multidimensional Transparency.
IEEE Trans. Hum. Mach. Syst., August, 2023

2021
Typology of Manufacturing Digital Twins: A First Step Towards a Deployment Methodology.
Proceedings of the Service Oriented, Holonic and Multi-agent Manufacturing Systems for Industry of the Future, 2021

2012
A design approach dedicated to network-based and conflict-free parallel interleavers.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A methodology based on Transportation problem modeling for designing parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2011

2010
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Bitwidth-aware high-level synthesis for designing low-power DSP applications.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Static Address Generation Easing: a design methodology for parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2010

Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.
J. Signal Process. Syst., 2009

2008
Estimation et optimisation de la consommation des mémoires.
Tech. Sci. Informatiques, 2008

2007
Constrained algorithmic IP design for system-on-chip.
Integr., 2007

Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels
CoRR, 2007

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A design flow dedicated to multi-mode architectures for DSP applications.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A design methodology for space-time adapter.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system.
Proceedings of the 15th European Signal Processing Conference, 2007

Application of a design space exploration tool to enhance interleaver generation.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
G729 Voice Decoder Design.
J. VLSI Signal Process., 2006

A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embed. Comput. Syst., 2006

Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems.
Signal Process., 2006

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI
CoRR, 2006

Memory Aware High-Level Synthesis for Embedded Systems
CoRR, 2006

A Memory Aware High Level Synthesis Too
CoRR, 2006

Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power
CoRR, 2006

Design Space Exploration of DSP Applications Based on Behavioral Description Models.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications.
EURASIP J. Adv. Signal Process., 2005

DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

High-level synthesis under I/O timing and memory constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

SystemCmantic: A high level Modelling and Co-Design Framework.
Proceedings of the Forum on specification and Design Languages, 2005

Pipelined memory controllers for DSP real-time applications handling unpredictable data accesses.
Proceedings of the 13th European Signal Processing Conference, 2005

C-based rapid prototyping for digital signal processing.
Proceedings of the 13th European Signal Processing Conference, 2005

High-Level Synthesis in Latency Insensitive System Methodology.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Synchronization Processor Synthesis for Latency Insensitive Systems.
Proceedings of the 2005 Design, 2005

2004
Synthèse architecturale d'applications temps réel pour technologies submicroniques.
Tech. Sci. Informatiques, 2004

Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur.
Ann. des Télécommunications, 2004

SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.
Proceedings of the Integrated Circuit and System Design, 2004

A Memory Aware High Level Synthesis Tool .
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Reed-Solomon behavioral virtual component for communication systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A memory aware behavioral synthesis tool for real-time VLSI circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A Complete Methodology for Memory Optimization in DSP Applications.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Memory Aware HLS and the Implementation of Ageing Vectors.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors.
Proceedings of the 2004 Design, 2004

Memory accesses management during high level synthesis.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT.
J. VLSI Signal Process., 2003

Power Consumption Modeling and Characterization of the TI C6201.
IEEE Micro, 2003

Communication and Timing Constraints Analysis for IP Design and Integration.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A simulation based approach for incorporating virtual components IP cores into multimedia systems design.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration.
Proceedings of the 2003 Design, 2003

2002
Power Consumption Estimation of a C Program for Data-Intensive Applications.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor.
Proceedings of the High Performance Computing, 4th International Symposium, 2002

A design methodology for IP integration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

High-level design verification using Taylor Expansion Diagrams: first results.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

IP cores integration in DSP System-on-chip designs.
Proceedings of the 11th European Signal Processing Conference, 2002

A design methodology for integrating IP into SOC systems.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
A Vision System on Chip for Industrial Control.
Proceedings of the SOC Design Methodologies, 2001

A smart "single line" pixel sensor for industrial vision.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Architectural synthesis of digital signal processing applications dedicated to submicron technologies.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller.
J. VLSI Signal Process., 1999

Architectural Synthesis with Interconnection Cost Control.
Proceedings of the VLSI: Systems on a Chip, 1999

Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Adaptive filters implementation performances under power dissipation constraint.
Proceedings of the 9th European Signal Processing Conference, 1998

1997
Hardware interface design for real time embedded systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1993
GAUT: An architectural synthesis tool for dedicated signal processors.
Proceedings of the European Design Automation Conference 1993, 1993


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