Sudipto Chakraborty

Orcid: 0000-0001-9884-5850

According to our database1, Sudipto Chakraborty authored at least 24 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Cryogenic CMOS: design considerations for future quantum computing systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023


2022
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Phase Noise Analysis of Separately Driven Ring Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas.
IEEE J. Solid State Circuits, 2022

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology.
IEEE J. Solid State Circuits, 2022

A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022



2021
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals.
IEEE Trans. Circuits Syst., 2020

2017
High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2012
A low power low phase noise fractional-N synthesizer with linearization and mismatch noise shaping techniques for sub-GHz multi-band transceiver with narrow channel spacing.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Multi-band, multi-mode, low-power CMOS receiver front-end for sub-GHz ISM/SRD band with narrow channel spacing.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
Fully Wireless Implantable Cardiovascular Pressure Monitor Integrated with a Medical Stent.
IEEE Trans. Biomed. Eng., 2010

Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications.
IEEE J. Solid State Circuits, 2008

2005
A low distortion, current feedback, programmable gain amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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