Fujun Bai
Orcid: 0000-0002-7971-5986
According to our database1,
Fujun Bai authored at least 10 papers
between 2017 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
A Reliable ESD 3D-Integrated Design and Simulation (3D-IDS) Methodology for Wafer-on-Wafer Stacked DRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026
A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators.
CoRR, April, 2026
CoRR, March, 2026
A 1.2GHz 12.77GB/s/mm<sup>2</sup> 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025
2023
Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory.
Sci. China Inf. Sci., April, 2023
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2023
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Remote. Sens., 2022
2017
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power.
Proceedings of the 12th IEEE International Conference on ASIC, 2017