Yi Kang

According to our database1, Yi Kang authored at least 66 papers between 1998 and 2024.

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Bibliography

2024
AD<sup>2</sup>VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.
IEEE Trans. Computers, January, 2024

2023
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources.
ACM Trans. Design Autom. Electr. Syst., November, 2023

Ghost key distribution under mutual authentication mechanism.
Inf. Sci., September, 2023

BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Gradient distribution-aware INT8 training for neural networks.
Neurocomputing, July, 2023

Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

Visual cryptography based on ghost imaging and Hadamard transform.
Quantum Inf. Process., February, 2023

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., January, 2023

Self-Supervised Node Classification with Strategy and Actively Selected Labeled Set.
Entropy, January, 2023

DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems.
ACM Trans. Design Autom. Electr. Syst., 2023

Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems.
IEEE Trans Autom. Sci. Eng., 2023

Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits.
CoRR, 2023

IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product.
CoRR, 2023

AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect.
CoRR, 2023

BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array.
CoRR, 2023

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM.
CoRR, 2023

Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity.
CoRR, 2023

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

An FPGA-Based Efficient NTT Accelerator for Post-Quantum Cryptography CRYSTALS-Kyber.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

FlsGraph: A Parallel Architecture for Large-scale Graph Processing.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

MF-DSNN:An Energy-efficient High-performance Multiplication-free Deep Spiking Neural Network Accelerator.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

HNSG - A SNN Training Method Ultilizing Hidden Network.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips.
ACM Trans. Design Autom. Electr. Syst., 2022

Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Real-time infrared small target detection network and accelerator design.
Integr., 2022

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs.
CoRR, 2022

Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks.
CoRR, 2022

Multi-scale Lightweight Neural Network for Real-Time Object Detection.
Proceedings of the PRICAI 2022: Trends in Artificial Intelligence, 2022

PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

Adaptive Turbulence Channel Equalization Based on Neural Network.
Proceedings of the 14th IEEE International Conference on Advanced Infocomm Technology, 2022

Demonstration of 8Gb/s 4-PAM Signal All-optical Wavelength Conversion Transmission under Simulated Atmospheric Laser Communication Network.
Proceedings of the 14th IEEE International Conference on Advanced Infocomm Technology, 2022

DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection.
Proceedings of the Data Mining and Big Data - 7th International Conference, 2022

2021
Rapidly Decoding Image Categories From MEG Data Using a Multivariate Short-Time FC Pattern Analysis Approach.
IEEE J. Biomed. Health Informatics, 2021

A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021

A Low-latency NoC Router Priority Scheme for BFS algorithm.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Corona Virus Disease 2019 Respiratory Cycle Detection Based on Convolutional Neural Network.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A Low Power Branch Prediction for Deep Learning on RISC-V Processor.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Stargate: a data source connector based on spark SQL.
Proceedings of the 2nd International Conference on Machine Learning and Soft Computing, 2018

AI Drives Domain Specific Processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2014
The Interactive Design and Performance Study of Instrument Panels Based on the Single-Handed Keyboard Mouse.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2012
FlexRAM: Toward an advanced Intelligent Memory system.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2009
A novel system multiplexing and program element identification scheme.
IEEE Trans. Consumer Electron., 2009

2008
A fast region-based inter mode selection algorithm.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
Unequal error protection based on objective video evaluation model.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

A Scheme for System Multiplexing and Program Component Identification.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

1999
An Intelligent Memory for Data -Parallel Applications
PhD thesis, 1999

1998
An IRAM architecture for image analysis and pattern recognition.
Proceedings of the Fourteenth International Conference on Pattern Recognition, 1998

Use IRAM for Rasterization.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998


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