Qiwei Ren
According to our database1,
Qiwei Ren
authored at least 9 papers
between 2015 and 2023.
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Bibliography
2023
Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory.
Sci. China Inf. Sci., April, 2023
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2023
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE/CIC International Conference on Communications in China, 2023
2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2017
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015