Xiping Jiang

Orcid: 0000-0002-7942-9576

According to our database1, Xiping Jiang authored at least 10 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Full-Stack Performance Evaluation Infrastructure for 3D-DRAM-based LLM Accelerators.
CoRR, April, 2026

Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator.
CoRR, March, 2026

A 1.2GHz 12.77GB/s/mm<sup>2</sup> 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025

Accurate positioning system in complex environment based on Beidou dual frequency differential positioning technology.
Int. J. Inf. Commun. Technol., 2025

2023
Novel Diagnosis Method for GIS Mechanical Defects Based on an Improved Lightweight CNN Model With Load Adaptive Matching.
IEEE Trans. Ind. Informatics, November, 2023

Research on Field Source Characteristics of Leakage Current of Arrester Based on TMR Sensor.
Sensors, 2023

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021


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