Fengguo Zuo

According to our database, Fengguo Zuo authored at least 4 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A 1.2GHz 12.77GB/s/mm² 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications.

Yue Cao, Jinghao Jiang, Haijun Jiang, Qian Zhang, Xuanzhi Liu, Jinhui Cheng, Zhongze Han, Xiping Jiang, Fengguo Zuo, Song Wang, Fujun Bai, Yixin Guo, Chunmeng Dou, Jianguo Yang, Hangbing Lv, Qi Liu, Ming Liu

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2023

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.

Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

184QPS/W 64Mb/mm²3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration.

Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021