Mustafa Badaroglu

According to our database, Mustafa Badaroglu authored at least 39 papers between 1999 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents.

Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021

A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network.

Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2020

Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited).

Mustafa Badaroglu

Proceedings of the SLIP '20: System-Level Interconnect, 2020

2018

Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond.

Mustafa Badaroglu

J. Low Power Electron., 2018

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics.

Farshad Firouzi, Amir M. Rahmani, Kunal Mankodiya, Mustafa Badaroglu, Geoff V. Merrett, P. Wong, Bahar J. Farahani

Future Gener. Comput. Syst., 2018

Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare.

Bahar J. Farahani, Farshad Firouzi, Victor I. Chang, Mustafa Badaroglu, Nicholas Constant, Kunal Mankodiya

Future Gener. Comput. Syst., 2018

2017

Sustaining Moore's Law with 3D Chips.

Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini

Computer, 2017

Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications.

Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, P. R. Chidi Chidambaram, Suman Datta

Proceedings of the 47th European Solid-State Device Research Conference, 2017

PPAC scaling enablement for 5nm mobile SoC technology.

Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, P. R. Chidi Chidambaram

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.

Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, P. Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Interconnect-aware device targeting from PPA perspective.

Mustafa Badaroglu, Jeff Xu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Holistic technology optimization and key enablers for 7nm mobile SoC.

Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, P. Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap

Proceedings of the Symposium on VLSI Circuits, 2015

2014

More Moore landscape for system readiness - ITRS2.0 requirements.

Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, SungGeun Kim, Gerhard Klimeck, Chorng-Ping Chang, Charles Cheung, Yuzo Fukuzaki

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.

Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2010

A Cascadable Random Neural Network Chip with Reconfigurable Topology.

Mustafa Badaroglu, Ugur Halici, Isik Aybay, Cuneyt Cerkez

Comput. J., 2010

2008

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment.

Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier

Proceedings of the Design, Automation and Test in Europe, 2008

2007

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.

Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas

IEEE J. Solid State Circuits, 2007

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers.

Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke

Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Scalable Gate-Level Models for Power and Timing Analysis.

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

SWAN: high-level simulation methodology for digital substrate noise generation.

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

IEEE Trans. Very Large Scale Integr. Syst., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.

Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate.

Charlotte Soens, Geert Van der Plas, Mustafa Badaroglu, Piet Wambacq, Stéphane Donnay, Yves Rolain, Maarten Kuijk

IEEE J. Solid State Circuits, 2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.

Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke

EURASIP J. Wirel. Commun. Netw., 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.

Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.

Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Lakshmanan Balasubramanian, Kris Tiri, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man

IEEE J. Solid State Circuits, 2004

Digital Ground Bounce Reduction by Phase Modulation of the Clock.

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

Proceedings of the 2004 Design, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.

Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

Proceedings of the 41th Design Automation Conference, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies.

Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell

IEEE J. Solid State Circuits, 2003

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.

Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man

Proceedings of the ESSCIRC 2003, 2003

2002

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification.

Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man

IEEE J. Solid State Circuits, 2002

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits.

Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen, Hugo J. De Man

IEEE J. Solid State Circuits, 2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.

Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen

Proceedings of the 39th Design Automation Conference, 2002

2001

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.

Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

High-level simulation of substrate noise generation including power supply noise coupling.

Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens

Proceedings of the 37th Conference on Design Automation, 2000

1999

BANDIT: embedding analog-to-digital converters on digital telecom ASICs.

Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels, Ivo Bolsens, Yann A. Zinzius, Georges G. E. Gielen, Willy Sansen, Tony Fondén, Svante Signell

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999