Mustafa Badaroglu

According to our database1, Mustafa Badaroglu authored at least 29 papers between 2000 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond.
J. Low Power Electron., 2018

Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics.
Future Gener. Comput. Syst., 2018

Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare.
Future Gener. Comput. Syst., 2018

Sustaining Moore's Law with 3D Chips.
IEEE Computer, 2017

Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

PPAC scaling enablement for 5nm mobile SoC technology.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Interconnect-aware device targeting from PPA perspective.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Holistic technology optimization and key enablers for 7nm mobile SoC.
Proceedings of the Symposium on VLSI Circuits, 2015

More Moore landscape for system readiness - ITRS2.0 requirements.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A Cascadable Random Neural Network Chip with Reconfigurable Topology.
Comput. J., 2010

Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment.
Proceedings of the Design, Automation and Test in Europe, 2008

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.
J. Solid-State Circuits, 2007

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Scalable Gate-Level Models for Power and Timing Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.
EURASIP J. Wireless Comm. and Networking, 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Digital Ground Bounce Reduction by Phase Modulation of the Clock.
Proceedings of the 2004 Design, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

High-level simulation of substrate noise generation including power supply noise coupling.
Proceedings of the 37th Conference on Design Automation, 2000