Younghwi Yang

According to our database1, Younghwi Yang authored at least 15 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2017
Power-Gated 9T SRAM Cell for Low-Energy Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2015

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Dynamic mixed serial-parallel content addressable memory (DMSP CAM).
Int. J. Circuit Theory Appl., 2013

2012
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.
Proceedings of the International SoC Design Conference, 2012

Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


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