Jae-Koo Park
Orcid: 0009-0006-9240-4118
  According to our database1,
  Jae-Koo Park
  authored at least 10 papers
  between 2013 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2025
An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS.
    
  
    IEEE J. Solid State Circuits, February, 2025
    
  
A 4λ× 50-Gb/s Si Photonic WDM Transmitter with Code-Based Wavelength Calibration and Locking.
    
  
    Proceedings of the Optical Fiber Communications Conference and Exhibition, 2025
    
  
An 88-Gb/s/pin Single-Ended PAM-4 Transmitter in 28-nm CMOS With Duty-Cycle-Error and Quadrature-Phase-Error Correction Using Pre-Coded Data Patterns.
    
  
    Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025
    
  
    Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
    
  
  2023
A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS.
    
  
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
    
  
  2021
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2021
    
  
  2019
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.
    
  
    IEEE J. Solid State Circuits, 2019
    
  
  2018
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.
    
  
    Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
    
  
  2017
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.
    
  
    Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
    
  
  2013
Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2013