Jae-Seung Jeong
Orcid: 0000-0001-7386-4473Affiliations:
- Samsung Electronics, Memory Division, Hwaseong, Korea
- Sungkyunkwan University, Suwon, Korea (2016-2018)
According to our database1,
Jae-Seung Jeong authored at least 4 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2026
A 32-Gb/s 0.89-pJ/b Ground-Referenced PAM-4/NRZ Transceiver with Unidirectional Current Summation and Double Sampling.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023
2022
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021