Seunghan Woo

According to our database, Seunghan Woo authored at least 3 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

15.10 A Vertical-Cell-Transistor-Based 4F² DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding.

Hyunchul Yoon, Youngseok Park, Tae Jin Park, Suk Lae Kim, Seungjae Jung, Daesun Kim, Kyunghwan Kim, Yongjun Kim, KyuChang Kang, Bokyeon Won, Sang-Hoon Jung, Seunghan Woo, Donggeon Kim, Jonghyuk Kim, In Jung, Junsoo Kim, Jae-Joon Song, InCheol Nam, Young-Hun Seo, Sungsoo Yim, Jemin Park, Changsik Yoo, Sangjoon Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2024

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5^th-Generation 10nm DRAM Process.

IkJoon Choi, Seunghwan Hong, Kihyun Kim, Jeongsik Hwang, Seunghan Woo, Young-Sang Kim, Cheongryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, Ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byongwook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin, Young-Kyu Lee, Jang-Woo Ryu, Sangwoong Shin, Sungchul Park, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, SangJoon Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2021

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.

Ki Chul Chun, Yong-Ki Kim, Yesin Ryu, Jaewon Park, Chi Sung Oh, Young-Yong Byun, So-Young Kim, Dong-Hak Shin, Jun Gyu Lee, Byung-Kyu Ho, Min-Sang Park, Seong-Jin Cho, Seunghan Woo, Byoung-Mo Moon, Beomyong Kil, Sungoh Ahn, Jae Hoon Lee, Sooyoung Kim, Seouk-Kyu Choi, Jae-Seung Jeong, Sung-Gi Ahn, Jihye Kim, Jun Jin Kong, Kyomin Sohn, Nam Sung Kim, Jung-Bae Lee

IEEE J. Solid State Circuits, 2021