We stand with Ukraine

We stand with Ukraine

Yesin Ryu

Orcid: 0000-0002-2678-7396

According to our database¹, Yesin Ryu authored at least 13 papers between 2008 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Links

On csauthors.net:

Bibliography

2026

Cerberus: Cross-Layer ECC Co-Design for Robust and Efficient Memory Protection.

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CoRR, May, 2026

PIAT: Unleashing Memory Parallelism via Power-Interference-Aware Timing Control.

[DOI]

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IEEE Comput. Archit. Lett., 2026

RowArmor: Efficient and Comprehensive Protection Against DRAM Disturbance Attacks.

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Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

2025

PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup.

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Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

LEAP: LLW RowHammer Mitigation System.

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Proceedings of the 21st International SoC Design Conference, 2024

Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers.

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Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.

[DOI]

IEEE J. Solid State Circuits, 2023

2022

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features.

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.

[DOI]

IEEE J. Solid State Circuits, 2021

HBM3 RAS: Enhancing Resilience at Scale.

[DOI]

Sudhanva Gurumurthi

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Vilas Sridharan

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IEEE Comput. Archit. Lett., 2021

2020

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2008

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.

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Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

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