Yesin Ryu

Orcid: 0000-0002-2678-7396

According to our database1, Yesin Ryu authored at least 7 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
IEEE J. Solid State Circuits, 2023

2022

2021
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021

HBM3 RAS: Enhancing Resilience at Scale.
IEEE Comput. Archit. Lett., 2021

2020

2018

2008
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008


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