Taesik Na
Orcid: 0000-0003-2039-3772
According to our database1,
Taesik Na
authored at least 35 papers
between 2008 and 2023.
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Bibliography
2023
CoRR, 2023
2022
2021
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning.
IEEE J. Solid State Circuits, 2021
2020
Cross-Layer Noise Analysis in Smart Digital Pixel Sensors With Integrated Deep Neural Network.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020
WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Effect of Process Variations in Digital Pixel Circuits on the Accuracy of DNN based Smart Sensor.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
CAMEL: An Adaptive Camera With Embedded Machine Learning-Based Sensor Parameter Control.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Mixture of Pre-processing Experts Model for Noise Robust Deep Learning on Resource Constrained Platforms.
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 30th British Machine Vision Conference 2019, 2019
2018
PhD thesis, 2018
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
An Energy-Quality Scalable Wireless Image Sensor Node for Object-Based Video Surveillance.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Edge-Host Partitioning of Deep Neural Networks with Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms.
Proceedings of the 15th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Behavioral modeling of timing slack variation in digital circuits due to power supply noise.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
An energy-efficient wireless video sensor node with a region-of-interest based multi-parameter rate controller for moving object surveillance.
Proceedings of the 13th IEEE International Conference on Advanced Video and Signal Based Surveillance, 2016
2013
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
IEEE J. Solid State Circuits, 2013
2012
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2008
An ethernet switch architecture for bandwidth provision of broadband access networks.
IEEE Commun. Mag., 2008