Bozhi Yin

According to our database, Bozhi Yin authored at least 11 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.

Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow.

Zhongkai Wang, Minsoo Choi, John Charles Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Cryo-Compatible, Silicon Spoked-Ring Modulator in a 45nm CMOS Platform for 4K-to-Room-Temperature Optical Links.

Hayk Gevorgyan, Anatol Khilo, Derek Van Orden, Deniz Onural, Bozhi Yin, Mark T. Wade, Vladimir Marko Stojanovic, Milos A. Popovic

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

Electronic-Photonic Cryogenic Egress Link.

Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Anatol Khilo, Milos A. Popovic, Vladimir Marko Stojanovic

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020

A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators.

Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic

IEEE J. Solid State Circuits, 2020

A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS.

Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu

IEEE J. Solid State Circuits, 2020

2019

A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS.

Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die.

Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018

A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation.

Chang Liu, Bozhi Yin, Tingyu Yao, Nan Qi, Dan Li, Jingbo Shi, Juncheng Wang, Hu Shang, Rui Bai, Patrick Yin Chiang

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS.

Juncheng Wang, Xuefeng Chen, Shang Hu, Yaxin Cai, Rui Bai, Xin Wang, Yuanxi Zhang, Shenglong Zhuo, Chang Liu, Bozhi Yin, Jianxu Ma, Hao Yan, Jiangao Xuan, Milton Lu, Tao Xia, Nan Qi, Patrick Yin Chiang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.

Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017