Jingyu Wang
Orcid: 0000-0002-7160-4165Affiliations:
- Tsinghua University, Department of Electronic Engineering, Beijing, China
According to our database1,
Jingyu Wang
authored at least 17 papers
between 2019 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.
IEEE J. Solid State Circuits, May, 2024
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications.
IEEE J. Solid State Circuits, 2022
2021
High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning.
CoRR, 2020
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019