Nivard Aymerich

According to our database1, Nivard Aymerich authored at least 8 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021

2014
Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm.
Microelectron. J., 2014

2013
Systematic and random variability analysis of two different 6T-SRAM layout topologies.
Microelectron. J., 2013

Extending the fundamental error bounds for asymmetric error reliable computation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy.
Microprocess. Microsystems, 2012

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.
Integr., 2012

2011
New reliability mechanisms in memory design for sub-22nm technologies.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011


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