Junhao Shi

According to our database, Junhao Shi authored at least 14 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

In Situ Reconfigurable Continuum Robot with Varying Curvature Enabled by Programmable Tensegrity Building Blocks.

Jie Zhang, Junhao Shi, Junhai Huang, Qihuan Wu, Yuwen Zhao, Jinzhao Yang, Hamed Rajabi, Zhigang Wu, Haijun Peng, Jianing Wu

Adv. Intell. Syst., July, 2023

2022

A Predictive Model of Spindle Thermal Error Based on DCGAN.

Junhao Shi

Proceedings of the 8th International Conference on Mechatronics and Robotics Engineering, 2022

2021

A GAN-based data augmentation method for human activity recognition via the caching ability.

Junhao Shi, Decheng Zuo, Zhan Zhang

Internet Technol. Lett., 2021

2020

Transition Activity Recognition System based on Standard Deviation Trend Analysis.

Junhao Shi, Decheng Zuo, Zhan Zhang

Sensors, 2020

Sensor-based activity recognition independent of device placement and orientation.

Junhao Shi, Decheng Zuo, Zhan Zhang, Danyan Luo

Trans. Emerg. Telecommun. Technol., 2020

2011

A real-time bimanual 3D interaction method based on bare-hand tracking.

Junhao Shi, Mingmin Zhang, Zhigeng Pan

Proceedings of the 19th International Conference on Multimedia 2011, Scottsdale, AZ, USA, November 28, 2011

2007

Boolean Techniques in Testing of Digital Circuits (Boolesche Techniken zum Testen von digitale Schaltkreise)

Junhao Shi

PhD thesis, 2007

2006

Efficiency of Multi-Valued Encoding in SAT-based ATPG.

Görschwin Fey, Junhao Shi, Rolf Drechsler

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Bridging fault testability of BDD circuits.

Junhao Shi, Görschwin Fey, Rolf Drechsler

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Synthesis of fully testable circuits from BDDs.

Rolf Drechsler, Junhao Shi, Görschwin Fey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

BDD Circuit Optimization for Path Delay Fault Testability.

Görschwin Fey, Junhao Shi, Rolf Drechsler

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

MuTaTe: an efficient design for testability technique for multiplexor based circuits.

Rolf Drechsler, Junhao Shi, Görschwin Fey

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.

Junhao Shi, Görschwin Fey, Rolf Drechsler

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003