Karel Heyse

According to our database1, Karel Heyse authored at least 15 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure.
ACM Trans. Reconfigurable Technol. Syst., 2015

Identification of Dynamic Circuit Specialization Opportunities in RTL Code.
ACM Trans. Reconfigurable Technol. Syst., 2015

TCONMAP: Technology Mapping for Parameterised FPGA Configurations.
ACM Trans. Design Autom. Electr. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration.
Des. Autom. Embed. Syst., 2015

Estimating circuit delays in FPGAs after technology mapping.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Avoiding transitional effects in dynamic circuit specialisation on FPGAs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Improving reconfiguration speed for dynamic circuit specialization using placement constraints.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs.
Proceedings of the FPGA World Conference 2014, 2014

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Mapping logic to reconfigurable FPGA routing.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011


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