Oliver Pell

According to our database1, Oliver Pell authored at least 31 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
Automating Elimination of Idle Functions by Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2015

On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure.
ACM Trans. Reconfigurable Technol. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

2014
Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines.
IEEE Micro, 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Cross Resource Optimisation of Database Functionality across Heterogeneous Processors.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Finite-Difference Wave Propagation Modeling on Special-Purpose Dataflow Machines.
IEEE Trans. Parallel Distributed Syst., 2013

An FPGA-Based Data Flow Engine for Gaussian Copula Model.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Aspect driven compilation for dataflow designs.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Runtime adaptation on dataflow HPC platforms.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
Maximum Performance Computing with Dataflow Engines.
Comput. Sci. Eng., 2012

Exploiting run-time reconfiguration in stencil computation.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Dataflow supercomputing.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Surviving the end of frequency scaling with reconfigurable dataflow computing.
SIGARCH Comput. Archit. News, 2011

Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications.
IEEE Micro, 2011

Accelerating Large-Scale HPC Applications Using FPGAs.
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011

2010
Surviving the end of scaling of traditional micro processors in HPC.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2008
Finding Speedup in Parallel Processors.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

2007
FPGA-based Streaming Computation for Lattice Boltzmann Method.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006
Verification of FPGA Layout Generators in Higher-Order Logic.
J. Autom. Reason., 2006

Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Generating Parametrised Hardware Libraries from Higher-Order Descriptions.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
Quartz: a framework for correct and efficient reconfigurable design.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Resolving Quartz Overloading.
Proceedings of the Correct Hardware Design and Verification Methods, 2005


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