Kyprianos Papademetriou

Orcid: 0000-0001-8419-0814

According to our database1, Kyprianos Papademetriou authored at least 40 papers between 2001 and 2018.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2018
A Reconfigurable PID Controller.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Run-time management of systems with partially reconfigurable FPGAs.
Integr., 2017

2016
Efficient bandwidth regulation at memory controller for mixed criticality applications.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Address interleaving for low-cost NoCs.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

On-chip networks for mixed-criticality systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Security in MPSoCs: A NoC Firewall and an Evaluation Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Security Enhancements for building saturation-free, low-power NoC-based MPSoCs.
Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

Hardware Task Scheduling for Partially Reconfigurable FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Security Effectiveness and a Hardware Firewall for MPSoCs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGA.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

FASTER run-time reconfiguration management.
Proceedings of the International Conference on Supercomputing, 2013

The FASTER vision for designing dynamically reconfigurable systems.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

A low cost embedded real time 3D stereo matching system for surveillance applications.
Proceedings of the 13th IEEE International Conference on BioInformatics and BioEngineering, 2013

2012
Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Developing RFID-Based Systems for Security in Marine Transportations.
Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
Performance of partial reconfiguration in FPGA systems: A survey and a cost model.
ACM Trans. Reconfigurable Technol. Syst., 2011

Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

2010
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems.
IEEE Trans. Instrum. Meas., 2010

Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

2009
High-speed FPGA-based implementations of a Genetic Algorithm.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Implementation of a genetic algorithm on a virtex-ii pro FPGA.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2007
Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Low-Cost Real-Time 2-D Motion Detection Based on Reconfigurable Computing.
IEEE Trans. Instrum. Meas., 2006

Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
A 2-D motion detection model for low-cost embedded reconfigurable I/O devices.
IEEE Trans. Biomed. Eng., 2005

2004
A Case Study on Rapid Prototyping of Hardware Systems: The Effect of CAD Tool Capabilities, Design Flows, and Design Styles.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

2003
Adaptation of a low cost motion recognition system for custom operation from shrink-wrapped hardware.
Proceedings of the 2003 ACM SIGMM Workshop on Biometrics Methods and Applications, 2003

A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2001
Rapid Prototyping of a Reusable 4x4 Active ATM Switch Core with the PCI Pamette.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

A Reconfigurable Embedded Input Device for Kinetically Challenged Persons.
Proceedings of the Field-Programmable Logic and Applications, 2001

Architecture and Application of PLATO, A Reconfigurable Active Network Platform.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001


  Loading...