Kuba Raczkowski

According to our database1, Kuba Raczkowski authored at least 16 papers between 2009 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016

A Fractional-n subsampling PLL based on a digital-to-time converter.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016

9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter.
IEEE J. Solid State Circuits, 2015

2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3.
Proceedings of the ESSCIRC 2014, 2014

A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction.
Proceedings of the ESSCIRC 2014, 2014

2013
CMOS low-power transceivers for 60GHz multi Gbit/s communications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010
A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009


  Loading...