Charlotte Soens

According to our database1, Charlotte Soens authored at least 17 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

2017
A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication.
IEEE J. Solid State Circuits, 2016

13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

CMOS low-power transceivers for 60GHz multi Gbit/s communications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
A 40 nm LP CMOS PLL for high-speed mm-wave communication.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 2-mm<sup>2</sup> 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A 2mm<sup>2</sup> 0.1-to-5GHz SDR receiver in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS.
IEEE J. Solid State Circuits, 2008

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.
Proceedings of the 2005 Design, 2005

Substrate noise immune design of an LC-tank VCO using sensitivity functions.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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