Jonathan Borremans

According to our database1, Jonathan Borremans authored at least 37 papers between 2006 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Sensors, 2018

An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015
A generic read-out circuit for resistive transducers.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014

2013
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Generic Framework for Optimizing Digital Intensive Harmonic Rejection Receivers.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

2011
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers.
IEEE J. Solid State Circuits, 2011

A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

SAW-less software-defined radio transceivers in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 5 mm<sup>2</sup> 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform.
IEEE J. Solid State Circuits, 2010

A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2010

A 5mm<sup>2</sup> 40nm LP CMOS 0.1-to-3GHz multistandard transceiver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A plug-and-play wideband RF circuit ESD protection methodology: T-diodes.
Microelectron. Reliab., 2009

A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS.
IEEE J. Solid State Circuits, 2009

A 2-mm<sup>2</sup> 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA.
IEEE J. Solid State Circuits, 2009

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Low-cost feedback-enabled LNAs in 45nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS.
IEEE J. Solid State Circuits, 2008

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2008

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A Single-Inductor Dual-Band VCO in a 0.06mm<sup>2</sup> 5.6GHz Multi-Band Front-End in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
The Potential of FinFETs for Analog and RF Circuit Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


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