Joungho Kim

Orcid: 0000-0003-1376-0781

According to our database1, Joungho Kim authored at least 50 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to modeling signal and power integrity in 3D integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
RL4CO: an Extensive Reinforcement Learning for Combinatorial Optimization Benchmark.
CoRR, 2023

Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect.
Proceedings of the 20th International SoC Design Conference, 2023

DevFormer: A Symmetric Transformer for Context-Aware Device Placement.
Proceedings of the International Conference on Machine Learning, 2023

2022
Collaborative Distillation Meta Learning for Simulation Intensive Hardware Design.
CoRR, 2022

Transformer Network-based Reinforcement Learning Method for Power Distribution Network (PDN) Optimization of High Bandwidth Memory (HBM).
CoRR, 2022

2021
Learning Collaborative Policies to Solve NP-hard Routing Problems.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

2019
Low Leakage Electromagnetic Field Level and High Efficiency Using a Novel Hybrid Loop-Array Design for Wireless High Power Transfer System.
IEEE Trans. Ind. Electron., 2019

Smartwatch Strap Wireless Power Transfer System With Flexible PCB Coil and Shielding Material.
IEEE Trans. Ind. Electron., 2019

2018
EMI Reduction Methods in Wireless Power Transfer System for Drone Electrical Charger Using Tightly Coupled Three-Phase Resonant Magnetic Field.
IEEE Trans. Ind. Electron., 2018

High-Resolution Synthesized Magnetic Field Focusing for RF Barcode Applications.
IEEE Trans. Ind. Electron., 2018

Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Miniaturized and high-performance RF packages with ultra-thin glass substrates.
Microelectron. J., 2018

2017
Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
High-Frequency Temperature-Dependent Through-Silicon-Via (TSV) Model and High-Speed Channel Performance for 3-D ICs.
IEEE Des. Test, 2016

Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

Shielding structures for through silicon via (TSV) to active circuit noise coupling in 3D IC.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015

TSV-based current probing structure using magnetic coupling in 2.5D and 3D IC.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015

Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Active Si interposer for 3D IC integrations.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Modeling and analysis of defects in through silicon via channel for non-invasive fault isolation.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Noise coupling modeling and analysis of through glass via(TGV).
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Electromagnetic Compatibility of Resonance Coupling Wireless Power Transfer in On-Line Electric Vehicle System.
IEICE Trans. Commun., 2014

Analysis and optimization of a power distribution network in 2.5D IC with glass interposer.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

Fault detection and isolation of multiple defects in through silicon via (TSV) channel.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Coil Design and Shielding Methods for a Magnetic Resonant Wireless Power Transfer System.
Proc. IEEE, 2013

Signal integrity design of TSV and interposer in 3D-IC.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Design and measurement of a compact on-interposer passive equalizer for chip-to-chip high-speed differential signaling.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Modeling and analysis of open defect in through silicon via (TSV) channel.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Magnetic field coupling on analog-to-digital converter from wireless power transfer system in automotive environment.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Signal integrity modeling and measurement of TSV in 3D IC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Non-contact wafer-level TSV connectivity test methodology using magnetic coupling.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Eye-diagram simulation and analysis of a high-speed TSV-based channel.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Fault isolation of short defect in through silicon via (TSV) based 3D-IC.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Analysis of glass interposer PDN and proposal of PDN resonance suppression methods.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

2011
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.
Proceedings of the 48th Design Automation Conference, 2011

2010
Frequency-Dependent Transmission Line Model of a Stranded Coaxial Cable.
IEICE Trans. Electron., 2010

2008
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network.
IEICE Trans. Electron., 2008

Design of a Low-Noise UWB Transceiver SiP.
IEEE Des. Test Comput., 2008

2006
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.
IEEE J. Solid State Circuits, 2006

Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB.
IEICE Trans. Electron., 2006

Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array.
IEEE Des. Test Comput., 2006

2005
Modeling and Measurement of Mode-Conversion and Frequency Dependent Loss in High-Speed Differential Interconnections on Multilayer PCB.
IEICE Trans. Electron., 2005

Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


  Loading...