Luigi Pantisano

According to our database1, Luigi Pantisano authored at least 7 papers between 2005 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2025
Microprocessor Switching Activity Translation to AC Gate Oxide Wearout: Does it Matter? INTEL4 Meteor Lake Chip Activity Case Study.
Proceedings of the IEEE International Reliability Physics Symposium, 2025

2019
High Performance and Yield for Super Steep Retrograde Wells (SSRW) by Well Implant / Si-based Epitaxy on Advanced Technology FinFETs.
Proceedings of the Device Research Conference, 2019

2012
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2007
Mechanism of O<sub>2</sub>-anneal induced V<sub>fb</sub> shifts of Ru gated stacks.
Microelectron. Reliab., 2007

Reliability screening of high-k dielectrics based on voltage ramp stress.
Microelectron. Reliab., 2007

2005
On the data interpretation of the C-AFM measurements in the characterization of thin insulating layers.
Microelectron. Reliab., 2005

Potential remedies for the V<sub>T</sub>/V<sub>fb</sub>-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey.
Microelectron. Reliab., 2005


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