Luigi Pantisano

According to our database, Luigi Pantisano authored at least 6 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

High Performance and Yield for Super Steep Retrograde Wells (SSRW) by Well Implant / Si-based Epitaxy on Advanced Technology FinFETs.

U. Rana, D. P. Brunco, S. Raman, Dina H. Triyoso, M. W. Stoker, J. B. Johnson, Luigi Pantisano, K. D. Seo, M. Zhao, A. Reznicek, R. Krishnan, B. Moser, J. Freeman, L. Jang, Evgeny Kaganer

Proceedings of the Device Research Conference, 2019

2012

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.

Tommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, Mitsuhiro Togo, N. Horiguchi, Jérôme Mitard, Aaron Thean, Guido Groeseneken, Cor Claeys, Felice Crupi

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2007

Mechanism of O₂-anneal induced V_fb shifts of Ru gated stacks.

Z. Li, Tom Schram, Luigi Pantisano, A. Stesmans, Thierry Conard, S. Shamuilia, V. V. Afanasiev, A. Akheyar, Sven Van Elshocht, D. P. Brunco, W. Deweerd, Y. Naoki, P. Lehnen, Stefan De Gendt, Kristin De Meyer

Microelectron. Reliab., 2007

Reliability screening of high-k dielectrics based on voltage ramp stress.

A. Kerber, Luigi Pantisano, Anabela Veloso, Guido Groeseneken, Martin Kerber

Microelectron. Reliab., 2007

2005

On the data interpretation of the C-AFM measurements in the characterization of thin insulating layers.

J. Pétry, Wilfried Vandervorst, Luigi Pantisano, Robin Degraeve

Microelectron. Reliab., 2005

Potential remedies for the V_T/V_fb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey.

W. Deweerd, Vidya Kaushik, J. Chen, Y. Shimamoto, Tom Schram, L.-Å. Ragnarsson, Annelies Delabie, Luigi Pantisano, B. Eyckens, J. W. Maes

Microelectron. Reliab., 2005