Jérôme Mitard

According to our database1, Jérôme Mitard authored at least 18 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Automatic Prediction of Metal-Oxide-Semiconductor Field-Effect Transistor Threshold Voltage Using Machine Learning Algorithm.
Adv. Intell. Syst., January, 2023

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Detecting Transistor Defects in Medical Systems Using a Multi Model Ensemble of Convolutional Neural Networks.
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021

2019
CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Scalability comparison between raised- and embedded-SiGe source/drain structures for Si<sub>0.55</sub>Ge<sub>0.45</sub> implant free quantum well pFET.
Microelectron. Reliab., 2018

Scaling CMOS beyond Si FinFET: an analog/RF perspective.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Isolation of nanowires made on bulk wafers by ground plane doping.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016


2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2007
Initial and PBTI-induced traps and charges in Hf-based oxides/TiN stacks.
Microelectron. Reliab., 2007


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