M. Natarajan Iyer

According to our database1, M. Natarajan Iyer authored at least 9 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
A plug-and-play wideband RF circuit ESD protection methodology: T-diodes.
Microelectron. Reliab., 2009

2007
Transient voltage overshoot in TLP testing - Real or artifact?
Microelectron. Reliab., 2007

2006
Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs - Concepts, constraints and solutions.
Microelectron. Reliab., 2006

2005
ESD-RF co-design methodology for the state of the art RF-CMOS blocks.
Microelectron. Reliab., 2005

Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

RF ESD protection strategies - the design and performance trade-off challenges.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits.
Microelectron. Reliab., 2004

2003
High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.
Microelectron. Reliab., 2003

2002
Significance of the failure criterion on transmission line pulse testing.
Microelectron. Reliab., 2002


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