Dimitri Linten

According to our database1, Dimitri Linten authored at least 66 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
A BSIM-Based Predictive Hot-Carrier Aging Compact Model.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Physics-based device aging modelling framework for accurate circuit reliability assessment.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

On the impact of buffer and GaN-channel thickness on current dispersion for GaN-on-Si RF/mmWave devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
A Compact Physics Analytical Model for Hot-Carrier Degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

On the impact of mechanical stress on gate oxide trapping.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS.
IEEE J. Solid State Circuits, 2019

Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Full (V<sub>g</sub>, V<sub>d</sub>) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

New Insights into the Imprint Effect in FE-HfO2 and its Recovery.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLP.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the {V<sub>G</sub>, V<sub>D</sub>} bias space.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
A Cautionary Note When Looking for a Truly Reconfigurable Resistive RAM PUF.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Comphy - A compact-physics framework for unified modeling of BTI.
Microelectron. Reliab., 2018

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectron. Reliab., 2018

New methodology for modelling MOL TDDB coping with variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

A multi-bit/cell PUF using analog breakdown positions in CMOS.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Self-heating-aware CMOS reliability characterization using degradation maps.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
ESD characterisation of a-IGZO TFTs on Si and foil substrates.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Tunable ESD clamp for high-voltage power I/O pins of a battery charge circuit in mobile applications.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC.
Microelectron. Reliab., 2016

2015

ESD characterization of planar InGaAs devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of local interconnects on ESD design.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Off-state stress degradation mechanism on advanced p-MOSFETs.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

ESD protection diodes in optical interposer technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Processing active devices on Si interposer and impact on cost.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013
Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool?
IEEE Trans. Instrum. Meas., 2009

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes.
Microelectron. Reliab., 2009

A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA.
IEEE J. Solid State Circuits, 2009

2008
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
The Potential of FinFETs for Analog and RF Circuit Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Implementation of plug-and-play ESD protection in 5.5GHz 90nm RF CMOS LNAs - Concepts, constraints and solutions.
Microelectron. Reliab., 2006

2005
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS.
IEEE J. Solid State Circuits, 2005

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors.
IEEE J. Solid State Circuits, 2005

Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

RF ESD protection strategies - the design and performance trade-off challenges.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Extended Subspace Identification of Improper Linear Systems.
Proceedings of the 2004 Design, 2004

A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004


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