Mahdi Nazm Bojnordi

Orcid: 0000-0002-1496-5650

According to our database1, Mahdi Nazm Bojnordi authored at least 41 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Monarch: A Durable Polymorphic Memory for Data Intensive Applications.
IEEE Trans. Computers, February, 2023

Compressed Geometric Arrays for Point Cloud Processing.
IEEE Trans. Multim., 2023

XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays.
IEEE Micro, 2023

2022
Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory.
IEEE Trans. Computers, 2022

2021
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

G-Arrays: Geometric Arrays for Efficient Point Cloud Processing.
Proceedings of the IEEE International Conference on Acoustics, 2021

Memristive Data Ranking.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
AxMAP: Making Approximate Adders Aware of Input Patterns.
IEEE Trans. Computers, 2020

STFL-DDR: Improving the Energy-Efficiency of Memory Interface.
IEEE Trans. Computers, 2020

RedCache: Reduced DRAM Caching.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data.
IEEE Trans. Computers, 2019

ReTagger: An Efficient Controller for DRAM Cache Architectures.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories.
IEEE Trans. Computers, 2018

Soft Realization: a Bio-inspired Implementation Paradigm.
CoRR, 2018

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
The Memristive Boltzmann Machines.
IEEE Micro, 2017

Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures.
Proceedings of the 5th International Workshop on Energy Efficient Supercomputing, 2017

Large Scale Data Clustering Using Memristive k-Median Computation.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Enabling energy efficient Hybrid Memory Cube systems with erasure codes.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient data movement with sparse transition encoding.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013
A programmable memory controller for the DDRx interfacing standards.
ACM Trans. Comput. Syst., 2013

Programmable DDRx Controllers.
IEEE Micro, 2013

DESC: energy-efficient data exchange using synchronized counters.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
PARDIS: A programmable memory controller for the DDRx interfacing standards.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2008
An Efficient and Extendable Modeling Approach for VLIW DSP Processors.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications.
Proceedings of the 15th International Symposium on Modeling, 2007

Simulation of Voice Processing Applications through VLIW DSP Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
An Efficient Deblocking Filter with Self-Transposing Memory Architecture For H.264/AVC.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

A concurrent testing method for NoC switches.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A Fast Two Dimensional Deblocking Filter for H.264/AVC Video Coding.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Efficient Hardware Implementation for H.264/AVC Motion Estimation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Self-Transposing Memory Structure for 32-bit Video Processors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Clocking Scheme for On-Chip Communications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Dual Mode Architecture for Deblocking Filtering in H.264/AVC Video Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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