Manolis Kaliorakis

According to our database, Manolis Kaliorakis authored at least 25 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

GMSA: A Digital Twin Application for Maritime Route and Event Forecasting.

Georgios Grigoropoulos, Giannis Spiliopoulos, Ilias Chamatidis, Manolis Kaliorakis, Alexandros Troupiotis-Kapeliaris, Marios Vodas, Evangelia Filippou, Eva Chondrodima, Nikos Pelekis, Yannis Theodoridis, Dimitris Zissis, Konstantina Bereta

Proceedings of the Proceedings 27th International Conference on Extending Database Technology, 2024

A Scalable System for Maritime Route and Event Forecasting.

Georgios Grigoropoulos, Giannis Spiliopoulos, Ilias Chamatidis, Manolis Kaliorakis, Alexandros Troupiotis-Kapeliaris, Marios Vodas, Evangelia Filippou, Eva Chondrodima, Nikos Pelekis, Yannis Theodoridis, Dimitris Zissis, Konstantina Bereta

Proceedings of the Proceedings 27th International Conference on Extending Database Technology, 2024

2023

A Digital Twin for Maritime Situational Awareness.

Alexandros Troupiotis-Kapeliaris, Giannis Spiliopoulos, Georgios Grigoropoulos, Evangelia Filippou, Ilias Chamatidis, Marios Vodas, Manolis Kaliorakis, Dimitris Zissis

Proceedings of the IEEE/ACM 10th International Conference on Big Data Computing, 2023

2021

A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs.

George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Greg Favor, Kumar Sankaran, Shidhartha Das

CoRR, 2021

2019

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.

Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo

IEEE Trans. Computers, 2019

2018

Methodologies for accelerated analysis of the reliability and the energy efficiency levels of modern microprocessor architectures

Manolis Kaliorakis

PhD thesis, 2018

Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions.

Manolis Kaliorakis, Athanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos

IEEE Comput. Archit. Lett., 2018

Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs.

George Papadimitriou, Athanasios Chatzidimitriou, Manolis Kaliorakis, Yannos Vastakis, Dimitris Gizopoulos

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.

Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo

Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.

Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Performance-aware reliability assessment of heterogeneous chips.

Athanasios Chatzidimitriou, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Harnessing voltage margins for energy efficiency in multicore CPUs.

George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment.

Manolis Kaliorakis, Dimitris Gizopoulos, Ramon Canal, Antonio González

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Voltage margins identification on commercial x86-64 multicore microprocessors.

George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.

Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Maurizio Iacaruso, Mauro Pipponzi, Riccardo Mariani, Stefano Di Carlo

Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

2016

Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level.

Sotiris Tselonis, Manolis Kaliorakis, Nikos Foutris, George Papadimitriou, Dimitris Gizopoulos

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cross-layer system reliability assessment framework for hardware faults.

Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale

Proceedings of the 2016 IEEE International Test Conference, 2016

2015

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.

Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo

Microprocess. Microsystems, 2015

Bayesian network early reliability evaluation analysis for both permanent and transient faults.

Alessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Differential Fault Injection on Microarchitectural Simulators.

Manolis Kaliorakis, Sotiris Tselonis, Athanasios Chatzidimitriou, Nikos Foutris, Dimitris Gizopoulos

Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

A Bayesian model for system level reliability estimation.

Alessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo

Proceedings of the 20th IEEE European Test Symposium, 2015

Accelerated microarchitectural Fault Injection-based reliability assessment.

Manolis Kaliorakis, Sotiris Tselonis, Athanasios Chatzidimitriou, Dimitris Gizopoulos

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014

Accelerated online error detection in many-core microprocessor architectures.

Manolis Kaliorakis, Mihalis Psarakis, Nikos Foutris, Dimitris Gizopoulos

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Versatile architecture-level fault injection framework for reliability evaluation: A first report.

Nikos Foutris, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013

Online error detection in multiprocessor chips: A test scheduling study.

Manolis Kaliorakis, Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013