Shyue-Kung Lu

According to our database, Shyue-Kung Lu authored at least 90 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

E³C Techniques for Protecting NAND Flash Memories.

Shyue-Kung Lu, Zeng-Long Tsai

J. Electron. Test., August, 2023

Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory.

Shyue-Kung Lu, Xin Dong

Proceedings of the IEEE International Test Conference in Asia, 2023

2022

Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories.

Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase

Proceedings of the IEEE International Test Conference, 2022

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits.

Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2022

Fault Resilience Techniques for Flash Memory of DNN Accelerators.

Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase

Proceedings of the IEEE International Test Conference in Asia, 2022

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators.

Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume

Proceedings of the IEEE 31st Asian Test Symposium, 2022

Fault Securing Techniques for Yield and Reliability Enhancement of RRAM.

Shyue-Kung Lu, Zhi-Jia Liu, Masaki Hashizume

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun

J. Electron. Test., 2021

2020

Fault-Aware Dependability Enhancement Techniques for Flash Memories.

Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi

IEEE Trans. Very Large Scale Integr. Syst., 2020

Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory.

Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

ECC Caching Techniques for Protecting NAND Flash Memories.

Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.

Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase

J. Electron. Test., 2019

A Static Method for Analyzing Hotspot Distribution on the LSI.

Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara

Proceedings of the IEEE International Test Conference in Asia, 2019

A Fault-Tolerant MPSoC For CubeSats.

Christian M. Fuchs, Pai H. Chou, Xiaoqing Wen, Nadia M. Murillo, Gianluca Furano, Stefan Holst, Antonis Tavoularis, Shyue-Kung Lu, Aske Plaat, Kostas Marinis

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes.

Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs.

Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth

IEICE Trans. Inf. Syst., 2018

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories.

Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume

J. Electron. Test., 2018

Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories.

Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume

J. Electron. Test., 2018

Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Progressive ECC Techniques for Phase Change Memory.

Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power.

Shyue-Kung Lu, Hung-Kai Huang

Proceedings of the International Test Conference in Asia, 2017

A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume.

Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type.

Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories.

Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.

Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories.

Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs.

Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth

IEICE Trans. Inf. Syst., 2016

Integrated Heterogeneous Infrastructure for Indoor Positioning.

Yi-Wei Ma, Jiann-Liang Chen, Yao-Hong Tsai, Pen-Chan Chou, Shyue-Kung Lu, Sy-Yen Kuo

Proceedings of the Security, Privacy and Anonymity in Computation, Communication and Storage, 2016

Online slack-time binning for IO-registered die-to-die interconnects.

Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng

Proceedings of the 2016 IEEE International Test Conference, 2016

Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories.

Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs.

Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen

IEEE Trans. Computers, 2015

Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs.

Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin, Masaki Hashizume

Proceedings of the VLSI Design, Automation and Test, 2015

Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories.

Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume

Proceedings of the 24th IEEE Asian Test Symposium, 2015

An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories.

Shyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Electrical interconnect test method of 3D ICs by injected charge volume.

Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit.

Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

A Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing.

Yi-Wei Ma, Jiann-Liang Chen, Ching-Hesign Chou, Shyue-Kung Lu

IEEE Syst. J., 2014

Efficient test length reduction techniques for interposer-based 2.5D ICs.

Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories.

Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

A built-in supply current test circuit for electrical interconnect tests of 3D ICs.

Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs.

Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs.

Tsu-Lin Li, Masaki Hashizume, Shyue-Kung Lu

IEICE Trans. Inf. Syst., 2013

Efficient test and repair architectures for 3D TSV-based random access memories.

Shyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Error-tolerance evaluation and design techniques for motion estimation computing arrays.

Shyue-Kung Lu, Ming-Chang Chen, Yen-Chi Chen

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories.

Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning

Proceedings of the 22nd Asian Test Symposium, 2013

Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs.

Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs.

Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Yield enhancement techniques for 3-dimensional random access memories.

Shyue-Kung Lu, Tin-Wei Chang, Han-Yu Hsu

Microelectron. Reliab., 2012

Improving Reusability of Test Symbols for Test Data Compression.

Shyue-Kung Lu, Ya-Chen Huang

J. Inf. Sci. Eng., 2012

Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs.

Shyue-Kung Lu, Tsu-Lin Li, Pony Ning

Proceedings of the 21st IEEE Asian Test Symposium, 2012

On test and repair of 3D random access memory.

Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores.

Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu

IEEE Des. Test Comput., 2011

2010

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.

Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Built-In Self-Repair Techniques for Heterogeneous Memory Cores.

Zhen-Yu Wang, Yi-Ming Tsai, Shyue-Kung Lu

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2007

Low-Power Built-In Self-Test Techniques for Embedded SRAMs.

Shyue-Kung Lu, Yuang-Cheng Hsiao, Chia-Hsiu Liu, Chun-Lin Yang

VLSI Design, 2007

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.

Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu

Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

2006

Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.

Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2006

Fault tolerance techniques for high capacity RAM.

Shyue-Kung Lu, Chih-Hsien Hsu

IEEE Trans. Reliab., 2006

A Scalable Port Forwarding for P2P-Based Wi-Fi Applications.

Ming-Wei Wu, Yennun Huang, Ing-Yi Chen, Shyue-Kung Lu, Sy-Yen Kuo

Proceedings of the Wireless Algorithms, 2006

Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.

Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy.

Shyue-Kung Lu, Chun-Lin Yang, Han-Wen Lin

Proceedings of the 5th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2006) and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering, 2006

2005

Design-for-testability and fault-tolerant techniques for FFT processors.

Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang

IEEE Trans. Very Large Scale Integr. Syst., 2005

A Multi-Faceted Approach towards Spam-Resistible Mail.

Ming-Wei Wu, Yennun Huang, Shyue-Kung Lu, Ing-Yi Chen, Sy-Yen Kuo

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

A BIRA algorithm for embedded memories with 2D redundancy.

Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004

Defect Level Prediction Using Multi-Model Fault Coverage.

Shyue-Kung Lu

IEICE Trans. Inf. Syst., 2004

Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.

Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.

Shyue-Kung Lu, Shih-Chang Huang

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model.

Shyue-Kung Lu, Mau-Jung Lu

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Testing and Diagnosis Techniques for LUT-Based FPGA's.

Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.

Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu

J. Inf. Sci. Eng., 2003

A Novel Built-In Self-Repair Approach for Embedded RAMs.

Shyue-Kung Lu

J. Electron. Test., 2003

Combinational circuit fault diagnosis using logic emulation.

Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs.

Shyue-Kung Lu, Fu-Min Yeh, Jen-Sheng Shih

VLSI Design, 2002

OBDD-based evaluation of k-terminal network reliability.

Fu-Min Yeh, Shyue-Kung Lu, Sy-Yen Kuo

IEEE Trans. Reliab., 2002

Enhancing Delay Fault Testability for Iterative Logic Array.

Shyue-Kung Lu, Chien-Hung Yeh

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.

Shyue-Kung Lu, Chien-Hung Yeh

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's.

Shyue-Kung Lu, Chung-Yang Chen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Fault-tolerance design of memory systems based on DBL structures.

Chih-Hsien Hsu, Shyue-Kung Lu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Novel Fault-Tolerant Techniques for High Capacity RAMs.

Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Built-In self-repair for divided word line memory.

Shyue-Kung Lu, Chih-Hsien Hsu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A Profit Evaluation System (PES) for logic cores at early design stage.

Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Testing Configurable LUT-Based FPGAs.

Shyue-Kung Lu, Jen-Sheng Shih

J. Inf. Sci. Eng., 2000

Built-in self-test and fault diagnosis for lookup table FPGAs.

Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Testable/Fault Tolerant FFT Processor Design.

Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A novel approach to testing LUT-based FPGAs.

Shyue-Kung Lu, Cheng-Wen Wu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Defect Level Prediction Using Multi-Model Fault Coverage.

Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1997

Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy.

Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu

IEEE Trans. Computers, 1997

1996

Cell delay fault testing for iterative logic arrays.

Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang

J. Electron. Test., 1996

1995

C-testable design techniques for iterative logic arrays.

Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 1995

1991

Designing Self-Testable Cellular Arrays.

Cheng-Wen Wu, Shyue-Kung Lu

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991