Meeta Sharma Gupta

According to our database1, Meeta Sharma Gupta authored at least 22 papers between 2004 and 2017.

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Bibliography

2017
Configurable Detection of SDC-causing Errors in Programs.
ACM Trans. Embed. Comput. Syst., 2017

2014
Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection.
Proceedings of the International Conference for High Performance Computing, 2014

GPUVolt: modeling and characterizing voltage noise in GPU architectures.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

SDCTune: A model for predicting the SDC proneness of an application for configurable protection.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Resilient Architecture Design for Voltage Variation
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01739-1, 2013

2012
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Power management of multi-core chips: Challenges and pitfalls.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Error Tolerance in Server Class Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Variation-Tolerant Microprocessor Architecture at Low Power.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Eliminating voltage emergencies via software-guided code transformations.
ACM Trans. Archit. Code Optim., 2010

Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity.
IEEE Micro, 2010

Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Tribeca: design for PVT variations with local recovery and fine-grained adaptation.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Voltage emergency prediction: Using signatures to reduce operating margins.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

An event-guided approach to reducing voltage noise in processors.
Proceedings of the Design, Automation and Test in Europe, 2009

Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
Proceedings of the 46th Design Automation Conference, 2009

2008
System level analysis of fast, per-core DVFS using on-chip switching regulators.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Towards a software approach to mitigate voltage emergencies.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005
Performance Implications of Periodic Checkpointing on Large-Scale Cluster Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Adaptive incremental checkpointing for massively parallel systems.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004


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