Reiley Jeyapaul

According to our database, Reiley Jeyapaul authored at least 20 papers between 2008 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

The gem5 Simulator: Version 20.0+.

Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian

CoRR, 2020

2019

Control Flow Checking or Not? (for Soft Errors).

Abhishek Rhisheekesan, Reiley Jeyapaul, Aviral Shrivastava

ACM Trans. Embed. Comput. Syst., 2019

2018

LASER: A hardware/software approach to accelerate complicated loops on CGRAs.

Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability.

Reiley Jeyapaul, Roberto Flores, Alfonso Ávila, Aviral Shrivastava

IEEE Trans. Very Large Scale Integr. Syst., 2017

Protecting Caches from Soft Errors: A Microarchitect's Perspective.

Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava

ACM Trans. Embed. Comput. Syst., 2017

2016

gemV: A validated toolset for the early exploration of system reliability.

Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee, Aviral Shrivastava

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

A Software Scheme for Multithreading on CGRAs.

Jared Pager, Reiley Jeyapaul, Aviral Shrivastava

ACM Trans. Embed. Comput. Syst., 2015

Guidelines to design parity protected write-back L1 data cache.

Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee, Aviral Shrivastava

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability.

Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee

IEEE Trans. Parallel Distributed Syst., 2014

Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors.

Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Enabling energy efficient reliability in embedded systems through smart cache cleaning.

Reiley Jeyapaul, Aviral Shrivastava

ACM Trans. Design Autom. Electr. Syst., 2013

2012

Soft errors: the hardware-software interface.

Kyoungwoo Lee, Aviral Shrivastava, Reiley Jeyapaul

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Enabling Multithreading on CGRAs.

Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula

Proceedings of the International Conference on Parallel Processing, 2011

UnSync: A Soft Error Resilient Redundant Multicore Architecture.

Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee

Proceedings of the International Conference on Parallel Processing, 2011

Smart cache cleaning: energy efficient vulnerability reduction in embedded processors.

Reiley Jeyapaul, Aviral Shrivastava

Proceedings of the 14th International Conference on Compilers, 2011

2010

Code Transformations for TLB Power Reduction.

Reiley Jeyapaul, Aviral Shrivastava

Int. J. Parallel Program., 2010

B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems.

Reiley Jeyapaul, Aviral Shrivastava

Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, 2010

Cache vulnerability equations for protecting data in embedded processor caches from soft errors.

Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

2009

Code Transformations for TLB Power Reduction.

Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.

Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008