Patrick Groeneveld

According to our database1, Patrick Groeneveld authored at least 30 papers between 1989 and 2022.

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Bibliography

2022
From Hard-Coded Heuristics to ML-Driven Optimization: New Frontiers for EDA.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021
ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020
Wafer scale interconnect and pathfinding for machine learning hardware (invited).
Proceedings of the SLIP '20: System-Level Interconnect, 2020

ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
Session details: Cyber-Physical Systems.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2016
Trailblazing Physical Design Flows: Ralph Otten's Impact on Design Automation.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Optimizing for Power, Speed, Cost and Emissions in Automotive Drivetrains.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

2012
Reality-driven physical synthesis.
Proceedings of the International Symposium on Physical Design, 2012

2010
SLIP: 10 years ago and 10 years from now.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Going with the flow: bridging the gap between theory and practice in physical design.
Proceedings of the 2010 International Symposium on Physical Design, 2010

2009
Oil fields, hedge funds, and drugs.
Proceedings of the 46th Design Automation Conference, 2009

2006
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2005
Is probabilistic congestion estimation worthwhile?
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Towards Integration of Quadratic Placement and Pin Assignment.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Post-Placement Pin Optimiztion.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004
Physical Synthesis: its struggle with Moore's law.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Probabilistic congestion prediction.
Proceedings of the 2004 International Symposium on Physical Design, 2004

How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the 2004 Design, 2004

2003
Nanometer design: place your bets.
Proceedings of the 40th Design Automation Conference, 2003

2002
Physical Design Challenges for Billion Transistor Chips.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Design Automation for Deepsubmicron: Present and Future.
Proceedings of the 2002 Design, 2002

Tools or users: which is the bigger bottleneck?
Proceedings of the 39th Design Automation Conference, 2002

2001
Automatic Hierarchical Design: Fantasy or Reality? (Panel).
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only).
Proceedings of the 2000 International Symposium on Physical Design, 2000

Design closure (panel session): hope or hype?
Proceedings of the 37th Conference on Design Automation, 2000

Timing closure: the solution and its problems.
Proceedings of ASP-DAC 2000, 2000

1993
Necessary and sufficient conditions for the routability of classical channels.
Integr., 1993

1990
A multiple layer contour-based gridless channel router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989
Wire ordering for detailed routing.
IEEE Des. Test, 1989


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