Erkan Alpman

According to our database1, Erkan Alpman authored at least 13 papers between 2009 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2018

A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


Overview of low-power wake-up radio design insights.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer.
IEEE J. Solid State Circuits, 2016

2015
A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012


2009
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009


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