Hung C. Ngo

According to our database1, Hung C. Ngo authored at least 9 papers between 1998 and 2009.

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Bibliography

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2006
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM J. Res. Dev., 2006

Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Controlled-Load Limited Switch Dynamic Logic Circuit.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

1998
Design methodology for a 1.0 GHz microprocessor.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998


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