Gianluca Durelli

According to our database1, Gianluca Durelli authored at least 40 papers between 2012 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A runtime controller for openCL applications on heterogeneous system architectures.
SIGBED Rev., 2018

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Exploiting FPGAs from Higher Level Languages A Signal Analysis Case Study.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

GPU-based computation for brain spatio-temporal networks definition.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Software implementation and hardware acceleration of retinal vessel segmentation for diabetic retinopathy screening tests.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Towards exascale computing with heterogeneous architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
On the design of autonomic techniques for runtime resource management in heterogeneous systems.
PhD thesis, 2016

Autonomic thread scaling library for QoS management.
SIGBED Rev., 2016

Using just-in-time code generation for transparent resource management in heterogeneous systems.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

Hardware Design Automation of Convolutional Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

On How to Improve FPGA-Based Systems Design Productivity via SDAccel.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Parallel Protein Identification Using an FPGA-Based Solution.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Workload-aware power optimization strategy for asymmetric multiprocessors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015
On how to efficiently accelerate brain network analysis on FPGA-based computing system.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An orchestrated approach to efficiently manage resources in heterogeneous system architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Power-awareness and smart-resource management in embedded computing systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

On how to extract breathing rate from PPG signal using wearable devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

A hardware approach to protein identification.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The autonomic operating system research project: achievements and future directions.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Towards a performance-as-a-service cloud.
Proceedings of the ACM Symposium on Cloud Computing, SOCC '13, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
TaBit: A framework for task graph to bitstream generation.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Automatic run-time manager generation for reconfigurable MPSoC architectures.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

On the automatic integration of hardware accelerators into FPGA-based embedded systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An open-source design and validation platform for reconfigurable systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

On the Development of a Runtime Reconfigurable Multicore System-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012


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