Sandro Sartoni
Orcid: 0000-0003-4609-9627
  According to our database1,
  Sandro Sartoni
  authored at least 9 papers
  between 2020 and 2023.
  
  
Collaborative distances:
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Bibliography
  2023
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
    
  
    Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
    
  
  2022
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.
    
  
    Proceedings of the 40th IEEE VLSI Test Symposium, 2022
    
  
    Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
    
  
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries.
    
  
    Proceedings of the IEEE European Test Symposium, 2022
    
  
  2021
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement.
    
  
    Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
    
  
  2020
    Proceedings of the 38th IEEE VLSI Test Symposium, 2020
    
  
    Proceedings of the IEEE International Test Conference, 2020
    
  
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs.
    
  
    Proceedings of the IEEE European Test Symposium, 2020