Paolo Bernardi
Orcid: 0000-0002-0985-9327
According to our database1,
Paolo Bernardi
authored at least 143 papers
between 1997 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
IEEE Trans. Computers, May, 2023
A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.
IEEE Access, 2023
A guided debugger-based fault injection methodology for assessing functional test programs.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
IEEE Access, 2022
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022
Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the IEEE European Test Symposium, 2022
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
Applicative System Level Test introduction to Increase Confidence on Screening Quality.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
A Machine Learning-based Approach to Optimize Repair and Increase Yield of Embedded Flash Memories in Automotive Systems-on-Chip.
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
J. Low Power Electron., 2018
J. Electron. Test., 2018
2017
J. Circuits Syst. Comput., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
An effective fault-injection framework for memory reliability enhancement perspectives.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Computers, 2016
Thermal issues in test: An overview of the significant aspects and industrial practice.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Software-based self-test techniques of computational modules in dual issue embedded processors.
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test.
IEEE Trans. Computers, 2014
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test.
J. Electron. Test., 2014
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
An effective approach to automatic functional processor test generation for small-delay faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis.
IEEE Trans. Instrum. Meas., 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
A Minimally Invasive Antenna for Microwave Ablation Therapies: Design, Performances, and Experimental Assessment.
IEEE Trans. Biomed. Eng., 2011
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test.
J. Electron. Test., 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Fault grading of software-based self-test procedures for dependable automotive applications.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Dependable Secur. Comput., 2010
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.
IET Comput. Digit. Tech., 2010
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2008
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
Proceedings of the Applications of Evolutionary Computing, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
Proceedings of the 12th European Test Symposium, 2007
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007
2006
IEEE Trans. Computers, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
2005
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 10th European Test Symposium, 2005
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electron. Test., 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
Proceedings of the 2004 Design, 2004
2003
Specific absorption rate and temperature elevation in a subject exposed in the far-field of radio-frequency sources operating in the 10-900-MHz range.
IEEE Trans. Biomed. Eng., 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
Proceedings of the 2003 Design, 2003
2001
A 915-MHz antenna for microwave thermal ablation treatment: physical design, computer modeling and experimental measurement.
IEEE Trans. Biomed. Eng., 2001
1997
Wirel. Networks, 1997
Assessment of the potential risk for humans exposed to millimeter-wave wireless LANs: the power absorbed in the eye.
Wirel. Networks, 1997
EMC-oriented full-wave modelling of passive MMIC structures for wireless applications.
Ann. des Télécommunications, 1997