Giseok Kim
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
Bibliography
2026
DPe-CIM: A 4T-1C Dual-Port eDRAM-Based Compute-in-Memory for Simultaneous Computing and Refresh With Adaptive Refresh and Data Conversion Reduction Scheme.
IEEE J. Solid State Circuits, June, 2026
A 3× Offset, 2.9× Power, 1.3× Sensing Time, and 4× Area Reduction Direct Input Transfer Offset Cancel DRAM IO Sense Amplifier With Static Current-Free Pre-Sensing.
IEEE J. Solid State Circuits, March, 2026
A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application.
IEEE J. Solid State Circuits, March, 2026
A 14 nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage With Minimal Power Overhead.
IEEE J. Solid State Circuits, February, 2026
2025
Asymmetric Voltage Latch Type and Ultra-Low Swing Bitline Sense Amplifiers for Low-Power High-Density 1R1W 8T SRAM in 14 nm FinFET.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing.
IEEE J. Solid State Circuits, June, 2025
SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025
2024
15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
DPe-CIM: A 4T1C Dual-Port eDRAM Compute-in-Memory for Simultaneous Computing and Refresh with Adaptive Refresh and Data Conversion Reduction Scheme.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Sensors, October, 2023
2022
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.
IEEE J. Solid State Circuits, 2022
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
IEEE Access, 2020
2015
Modeling a color-rendering operator for high dynamic range images using a cone-response function.
J. Electronic Imaging, 2015
2014
Proceedings of the 3DTV-Conference 2014: The True Vision, 2014