Ji-Yung Lin

Orcid: 0000-0001-9119-6069

According to our database1, Ji-Yung Lin authored at least 7 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020


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