Shufan Yang

According to our database1, Shufan Yang authored at least 26 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Rotational Blended Learning in Computer System Engineering Courses.
IEEE Trans. Education, 2019

A Secure Occupational Therapy Framework for Monitoring Cancer Patients' Quality of Life.
Sensors, 2019

A Highly Integrated Hardware/Software Co-Design and Co-Verification Platform.
IEEE Design & Test, 2019

A Load-Aware Clustering Model for Coordinated Transmission in Future Wireless Networks.
IEEE Access, 2019

2018
A neuro-inspired visual tracking method based on programmable system-on-chip platform.
Neural Computing and Applications, 2018

Radar for assisted living in the context of Internet of Things for Health and beyond.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

A Low Computational Approach for Assistive Esophageal Adenocarcinoma and Colorectal Cancer Detection.
Proceedings of the Advances in Computational Intelligence Systems, 2018

Activity Classification Using Raw Range and I & Q Radar Data with Long Short Term Memory Layers.
Proceedings of the 2018 IEEE 16th Intl Conf on Dependable, 2018

2017
An intelligible implementation of FastSLAM2.0 on a low-power embedded architecture.
EURASIP J. Emb. Sys., 2017

Unconstrained Face Detection and Open-Set Face Recognition Challenge.
CoRR, 2017

Presenting and Investigating the Efficacy of an Educational Interactive Mobile Application for British Sign Language Using Hand Gesture Detection Techniques.
Proceedings of the 16th World Conference on Mobile and Contextual Learning, 2017

Interactive Reading Using Low Cost Brain Computer Interfaces.
Proceedings of the Human-Computer Interaction - INTERACT 2017, 2017

Unconstrained Face Detection and Open-Set Face Recognition Challenge.
Proceedings of the 2017 IEEE International Joint Conference on Biometrics, 2017

2015
Modelling visual attention towards embodiment cognition on a reconfigurable and programmable system.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2013
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013

An Efficient Cursor Search Algorithm.
Computer and Information Science, 2013

2012
RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Fair Access to External Memory for Chip-multiprocessor.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

RIVER: Reconfigurable Pre-Synthesized-Streaming Architecture for Signal Processing on FPGAs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
A biologically plausible real-time spiking neuron simulation environment based on a multiple-FPGA platform.
SIGARCH Computer Architecture News, 2011

2009
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.
Fundam. Inform., 2009

Adaptive admission control on the SpiNNaker MPSoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
Virtual synaptic interconnect using an asynchronous network-on-chip.
Proceedings of the International Joint Conference on Neural Networks, 2008

Further Research and Comparison of Gaits for Compass-Like Biped and Kneed Passive Dynamic Walker.
Proceedings of the Intelligent Robotics and Applications, First International Conference, 2008

An admission control system for QoS provision on a best-effort GALS interconnect.
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008

2007
A GALS Infrastructure for a Massively Parallel Multiprocessor.
IEEE Design & Test of Computers, 2007


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