Thiago Copetti

Orcid: 0000-0001-7591-6484

According to our database1, Thiago Copetti authored at least 28 papers between 2012 and 2023.

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Bibliography

2023
Evaluating a New RRAM Manufacturing Test Strategy.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Characterization and Test of Intermittent Over RESET in RRAMs.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

2021
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.
J. Electron. Test., 2021

Review of Manufacturing Process Defects and Their Effects on Memristive Devices.
J. Electron. Test., 2021

A DfT Strategy for Detecting Emerging Faults in RRAMs.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Evaluating the Impact of Process Variation on RRAMs.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Improving the Detection of Undefined State Faults in FinFET SRAMs.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects.
J. Electron. Test., 2020

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2019
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects.
J. Electron. Test., 2019

A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects.
Proceedings of the IEEE Latin American Test Symposium, 2019

2018
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
Analysing NBTI Impact on SRAMs with Resistive Defects.
J. Electron. Test., 2017

Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Analyzing the behavior of FinFET SRAMs with resistive defects.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

2016
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits.
J. Electron. Test., 2016

NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time.
J. Electron. Test., 2016

Analyzing NBTI impact on SRAMs with resistive-open defects.
Proceedings of the 17th Latin-American Test Symposium, 2016

Gate-level modelling of NBTI-induced delays under process variations.
Proceedings of the 17th Latin-American Test Symposium, 2016

2015
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG.
Proceedings of the 16th Latin-American Test Symposium, 2015

NBTI-aware design of integrated circuits: a hardware-based approach.
Proceedings of the 16th Latin-American Test Symposium, 2015

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
An On-Chip Sensor to Monitor NBTI Effects in SRAMs.
J. Electron. Test., 2014

Hierarchical identification of NBTI-critical gates in nanoscale logic.
Proceedings of the 15th Latin American Test Workshop, 2014

2012
Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM.
Proceedings of the 13th Latin American Test Workshop, 2012

On-chip aging sensor to monitor NBTI effect in nano-scale SRAM.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012


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